May 2016 DocID026318 Rev 5 1/20

STM32F334x4/x6/x8

Errata sheet

STM32F334x4/x6/x8 Rev Z device limitations

Silicon identification

This errata sheet applies to revision Z of the STMicroelectronics STM32F334xx products.

These families feature an ARM

32-bit Cortex

-M4 FPU core, for which an errata notice is

also available (see Section 1 for details).

Section 2 gives a detailed description of the product silicon limit

ations.

The products are identifiable as shown in Table 1:

• By the revision code marked below the order code on the device package

• By the last three digits of the Internal o

rder code printed on the box label

The full list of part numbers is shown in Table 2.

Table 1. Device identification

(1)

1. The REV_ID bits in the DBGMCU_IDCODE register show the r

evision code of the device (see the

STM32F334xx reference manual for details on how to find the revision code).

(2)

Order code Revision code marked on device

STM32F334xx “

Z”

Table 2. Device summary

Reference Part number

STM32F334xx

STM32F334K4, STM32F334C4, STM32F334R4

STM32F334K6, STM32F334C6, STM32F334R6

STM32F334K8, STM32F334C8, STM32F334R8

2. Refer to datasheet for the device marking.

www.st.com

Contents STM32F334x4/x6/x8

2/20 DocID026318 Rev 5

Contents

1 ARM

32-bit Cortex

-M4 FPU core limitations . . . . . . . . . . . . . . . . . . . . 4

1.1 Cortex

-M4 FPU core interrupted loads to stack pointer can

cause erroneous behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 VDIV or VSQRT instructions might not complete correctly

when very short ISRs are used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 STM32F334xx silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.1 Wakeup sequence from Standby mode when using more than

one wakeup source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.2 Full JTAG configuration without NJTRST pin cannot be used . . . . . . . . . 8

2.1.3 CCM RAM write protection register SYSCFG_RCR not reset by

system reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 ADC peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.1 DMA Overrun in dual interleaved mode with single DMA channel . . . . . 9

2.2.2 Sampling time shortened in JAUTO autodelayed mode . . . . . . . . . . . . . 9

2.2.3 Injected queue of context is not available in case of JQM = 0 . . . . . . . . . 9

2.2.4 Load multiple not supported by ADC interface . . . . . . . . . . . . . . . . . . . 10

2.2.5 Possible voltage drop caused by a transitory phase when the ADC

is switching from a regular channel to an injected channel Rank 1 . . . . 10

2.2.6 Overrun flag may not be set if converted data are not read before

writing new data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2.7 ADC differential mode Common mode input range. . . . . . . . . . . . . . . . 11

2.3 SPI peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.3.1 SPI CRC may be corrupted when a peripheral connected to the same

DMA channel of the SPI is under DMA transaction near the end of

transfer or end of transfer ‘-1’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.2 BSY bit may stay high at the end of a SPI data transfer in slave mode . 12

2.4 I

C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4.1 10-bit slave mode: wrong direction bit value after Read header

reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4.2 10-bit combined with 7-bit slave mode: ADDCODE may indicate wrong

slave address detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.4.3 Wakeup frames may not wakeup the MCU mode when STOP mode

entry follows I

C enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.4.4 Wrong behaviors related with MCU Stop mode when wakeup from Stop

mode by I2C peripheral disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15