September 2021 ES0303 Rev 7 1/55
1
STM32L471xx
Errata sheet
STM32L471xx device errata
Applicability
This document applies to the part numbers of STM32L471xx devices s and the device
variants as stated in this page.
It gives a summary and a description of the device errata, with respect to the device
datasheet and reference manual RM0351.
Deviation of the real device behavior from the intended device behavior is considered to be
a device limitation. Deviation of the description in the reference manual or the datasheet
from the intended device behavior is considered to be a documentation erratum. The term
errata applies both to limitations and documentation errata.
Table 1. Device summary
Reference Part numbers
STM32L471xx
STM32L471QE, STM32L471QG, STM32L471RE, STM32L471RG
STM32L471VE, STM32L471VG, STM32L471ZE, STM32L471ZG
Table 2. Device variants
Reference
Silicon revision codes
Device marking
(1)
1. Refer to the device datasheet for details on how to identify this code on different types of
package.
REV_ID
(2)
2. The REV_ID[15:0] bit field of DBGMCU_IDCODE register (refer to the reference manual
RM0351).
STM32L471xx 4 0x1007
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Contents STM32L471xx
2/55 ES0303 Rev 7
Contents
1 Summary of device limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description of device limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.1 Interrupted loads to stack pointer can cause erroneous behavior . . . . . 13
2.1.2 VDIV or VSQRT instructions might not complete correctly
when very short ISRs are used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.3 Store immediate overlapping exception return operation
might vector to incorrect interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 FW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.1 Code segment unprotected if non-volatile data segment length is 0 . . . 16
2.2.2 Code and non-volatile data unprotected upon bank swap . . . . . . . . . . . 16
2.3 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.1 Write operation in the Flash memory while it is not ready
(Flash memory in power-down) is not correctly handled . . . . . . . . . . . . 17
2.3.2 The configuration of the I/Os not available in WLCSP package
can be modified by software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.3 SRAM2 read access while the SRAM2 hardware erase is ongoing
is not correctly supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.4 PH0/PH1 is controlled by the GPIOH registers when HSE is enabled . 17
2.3.5 PWR_CR4 register write access may not be completed if a
Low-power mode is entered just after the write operation . . . . . . . . . . . 18
2.3.6 HSI user trim is limited on some samples . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.7 Option byte loading can fail if MSI frequency is greater than 8 MHz . . . 19
2.3.8 PLL may not lock if VCO is below 96 MHz and temperature is
below 0 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.9 Full JTAG configuration without NJTRST pin cannot be used . . . . . . . . 20
2.3.10 MSIRDY flag issue preventing entry in low power mode . . . . . . . . . . . . 20
2.3.11 PCPROP area within a single Flash memory page becomes
unprotected at RDP change from level 1 to level 0 . . . . . . . . . . . . . . . . 21
2.3.12 Data Cache might be corrupted during Flash Read While Write
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.13 MSI frequency overshoot upon Stop mode exit . . . . . . . . . . . . . . . . . . . 22
2.3.14 Internal voltage reference corrupted upon Stop mode entry
with temperature sensing enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.15 OPAMP output: VDDA overconsumption . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.16 Spurious BOR when entering Stop mode after short Run sequence . . 23
