Introduction

This document gives a presentation of the core-coupled memory (CCM) SRAM available on STM32F3/STM32G4

microcontrollers and describes what is required to execute part of the application code from this memory region using different

toolchains.

The first section provides an overview of the CCM SRAM, while the next sections describe the steps required to execute part of

the application code from CCM SRAM using the following toolchains:

•

IAR Systems

IAR Embedded Workbench

•

Keil

MDK-ARM

• STMicroelectronics STM32CubeIDE and other GNU-based toolchains

The procedures described throughout the document are applicable to other SRAM regions such as the CCM data RAM of some

STM32F4 devices, or external SRAM.

Table 1 lists the STM32 microcontrollers used as examples for CCM SRAM.

Table 1. Applicable products

Reference Products

STM32F3/STM32G4

STM32F3

STM32F303 line, STM32F334 line

STM32F328C8, STM32F328K8, STM32F328R8

STM32F358CC, STM32F358RC, STM32F358VC

STM32F398RE, STM32F398VE, STM32F398ZE

STM32G4 STM32G4 Series

Use STM32F3/STM32G4 CCM SRAM with IAR Embedded Workbench

, Keil

MDK-ARM, STMicroelectronics STM32CubeIDE and other GNU-based toolchains

AN4296

Application note

AN4296 - Rev 5 - February 2021

For further information contact your local STMicroelectronics sales office.

www.st.com

1 Overview of STM32F3/STM32G4 CCM SRAM

This document applies to STM32F3/STM32G4 microcontrollers based on the Arm

Cortex

‑M core.

Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

1.1 Purpose

The CCM SRAM is tightly coupled with the Arm

Cortex

core, to execute the code at the maximum system clock

frequency without any wait-state penalty. This also brings a significant decrease of the critical task execution time,

compared to code execution from Flash memory.

The CCM SRAM is typically used for real-time and computation intensive routines, like the following:

• digital power conversion control loops (switch-mode power supplies, lighting)

• field-oriented 3-phase motor control

• real-time DSP (digital signal processing) tasks

When the code is located in CCM SRAM and data stored in the regular SRAM, the Cortex

‑M4 core is in the

optimum Harvard configuration. A dedicated zero-wait-state memory is connected to each of its I-bus and D-bus

(see the figures below) and can thus perform at 1.25 DMIPS/MHz, with a deterministic performance of 90 DMIPS

in STM32F3 and 213 DMIPS in STM32G4. This also guarantees a minimal latency if the interrupt service routines

are placed in the CCM SRAM.

Figure 1. STM32F3 device system architecture

FLTIF

SRAM

AHB dedicated

to GPIO ports

CCM

SRAM

RCC, TSC, CRC and

AHB to APB1 and APB2

ADCs

I-bus

S-bus

D-bus

DMA

Arm

Cortex-M4

GPDMA1

GPDMA2

FLASH

64 bits

ICODE

DCODE

BusMatrix-S

M1 M2 M3 M4

S4 S0S3 S1S2

AN4296

Overview of STM32F3/STM32G4 CCM SRAM

AN4296 - Rev 5

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