1 Summary of device errata
The following table gives a quick reference to the STM32H562xx/563xx/573xx device limitations and their status:
A = limitation present, workaround available
N = limitation present, no workaround available
P = limitation present, partial workaround available
“-” = limitation absent
Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround
may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the
rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on
the device or in only a subset of operating modes, of the function concerned.
Table 3. Summary of device limitations
Function Section Limitation
Status
Rev.
A
Rev.
Z
Rev.
X
Core 2.1.1
Access permission faults are prioritized over unaligned Device
memory faults
N N N
System
2.2.1 LSE crystal oscillator may be disturbed by transitions on PC13 N N N
2.2.2
Peripheral triggers connected to RTC wakeup timer interrupt instead
of RTC wakeup timer trigger signal
A A A
2.2.3 HSE not operational as oscillator N - -
2.2.4
Incorrect behavior of ICACHE refill from SRAM when an SRAM AHB
error occurs
N N N
2.2.5 Device cannot exit from Standby mode except by a power-on reset N - -
2.2.6 SRAMx_RST option bits have an immediate effect A A A
2.2.7 Additional consumption on PA11/PA12 in Stop and Standby modes A - -
2.2.8 Product state change is not supported on early samples P - -
2.2.9
Flash memory latency is increased during read-while-write (RWW)
operation
A A -
2.2.10
Product state regression is not possible when data flash memory is
enabled
N N -
2.2.11 Full JTAG configuration without NJTRST pin cannot be used A A A
2.2.12 BOOT0 pin is sensitive to electrostatic discharge N N -
2.2.13 Flash memory endurance is limited to 1 Kcycle N N -
2.2.14 SRAM2 is erased when the backup domain is reset A A A
2.2.15
Clearing IWDG_SW might result in debug authentication or ST-iRoT
failure
A A -
2.2.16
Clearing WWDG_SW might result in debug authentication or ST-iRoT
failure
A A A
2.2.17 LSE low drive mode is not functional N N N
2.2.18 Read from flash memory may fail in VOS2 and VOS1 range A A -
2.2.19 Partial regression may lead to incorrect device configuration A A -
2.2.20 Incorrect backup domain reset A A A
2.2.21
Debug not available when TrustZone
®
security is disabled and the
PRODUCT_STATE is iROT-Provisioned
A A A
2.2.22
Incorrect flash memory configuration on early STM32H562xG and
STM32H563xG devices
N N N
STM32H562xx/563xx/573xx
Summary of device errata
ES0565 - Rev 4
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