April 2020 AN4760 Rev 3 1/95
1
AN4760
Application note
Quad-SPI interface on STM32 microcontrollers and
microprocessors
Introduction
In order to manage a wide range of multimedia, richer graphics and other data-intensive
content, embedded applications evolve to offer more sophisticated features. These
sophisticated features require extra demands on the often limited micocontroller (MCU) and
microprocessor (MPU) on-chip memory.
The STM32 MCUs and MPUs will be referred to as STM32 devices in this document. The
devices that are concerned are listed in
Table 1: Applicable products
External parallel memories are used to extend the STM32 devices on-chip memory and
solve the memory size limitation. Usually this action compromises an increase in the pin
count and implies a more complex design.
To face these requirements, the STM32 devices embed an external memory interface
named Quad-SPI (see more details on
Table 2 on page 9). This interface allows the
connection of external compact-footprint Quad-SPI high-speed memories.This Quad-SPI
interface is used for data storage such as images, icons, or for code execution.
This application note describes the Quad-SPI interface on the STM32 devices and explains
how to use the module to configure, program, and read external Quad-SPI memory. It
describes some typical use cases to use the Quad-SPI interface based on some software
examples from the STM32Cube firmware package and from the STM32F7 Series
application notes.
For additional more detailed information about the products listed in the table below, refer to
the corresponding datasheets and reference manuals available from the STMicroelectronics
web site www.st.com.
Table 1. Applicable products
Type Products, lines and series
Microcontrollers
STM32F7 Series, STM32L4 Series
STM32F412, STM32F413/423, STM32F446, STM32F469/479,
STM32H743/753, STM32H750 Value line
STM32L4R5/S5, STM32L4R7/S7, STM32L4R9/S9
STM32WB55CC, STM32WB55CE, STM32WB55CG, STM32WB55RC,
STM32WB55RE, STM32WB55RG, STM32WB55VC, STM32WB55VE,
STM32WB55VG, STM32WB35CC, STM32WB35CE, STM32WB35CZ
Microprocessors STM32MP151x, STM32MP153x, STM32MP157x devices
www.st.com
Contents AN4760
2/95 AN4760 Rev 3
Contents
1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 QUADSPI availability and features across STM32 families . . . . . . . . . . . . 8
2.2 Quad-SPI benefits against classic SPI and parallel interfaces . . . . . . . . . 10
2.2.1 Main benefits of STM32 embedded Quad-SPI interface . . . . . . . . . . . . 10
2.3 QUADSPI in a smart architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.3.1 System architecture: STM32L4 Series . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.2 System architecture: STM32F4 Series . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.3 System architecture: STM32F7 Series . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.4 System architecture: STM32H7 Series . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.5 System architecture: STM32WB35xx and STM32WB55xx devices . . . 16
3 Quad-SPI interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Flexible frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.1 Instruction phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.2 Address phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.3 Alternate-byte phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.4 Dummy-cycle phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.5 Data phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 Multiple hardware-configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1 Single-SPI mode (classic SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.2 Dual-SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.3 Quad-SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.4 Dual-Flash memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.5 DDR and SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Three operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.1 Indirect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.2 Status-flag polling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.3 Memory-mapped mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4 Special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.1 Send instruction only-once (SIOO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.2 Delayed data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.3 Timeout counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
