1

Watchdog’s

2

WWDG features

• Window Watchdog can be activated by

Hardware (Option byte) or Software

(setting WDGA bit in CR register)

• Configurable time-window, can be

programmed to detect abnormally early or

late application behavior

• Conditional reset

– Reset when the down counter value

becomes less than 40h (T6=0)

– Reset if the down counter is reloaded

outside the time-window

• To prevent WWDG reset: write T[6:0] bits

at regular intervals while the counter

value is lower than the time-window value

(W[6:0])

• WWDG reset flag (in RST_SR) to inform when a

WWDG reset occurs

• Min-max timeout value @16MHz :

0.77ms/49.15ms by step of ~0.768ms

CM

P

W0 W1 W2 W3 W4 W5 W6

-

T0 T1 T2 T3 T4 T5 T6

WDGA

WWDG_CR

WWDG_WR

PRESCALER

(WDGTB)

6-Bit Down Counter

SYSCLK

(up to

16MHz)

Write WWDG_CR

comparator

= 1 when

T6:0 > W6:0

WWDG

Reset

Refresh

not allowed

Refresh

Window

T[6:0] CNT down counter

time

W[6:0]

3Fh

T6 bit

Reset