Introduction

The memory protection unit (MPU) in the Cortex

-M7 processor allows the modification of the Level 1 (L1) cache attributes by

region. The cache control is done globally by the cache control register, but the MPU can specify the cache mode and whether

the access to the region can be cached or not.

In some cases, the cached systems need to ensure data coherency between the core and the main memory when dealing with

shared data.

This application note describes the level 1 cache behavior and gives an example showing how to ensure data coherency in the

STM32F7 Series and STM32H7 Series when using the L1-cache.

For more details about the MPU and how to set the memory attributes according to the memory type and the cache policy, the

user can refer to the following documents available on http://www.st.com:

•

STM32F7 Series and STM32H7 Series Cortex

-M7 processor programming manual (PM0253).

• Managing memory protection unit (MPU) in STM32 MCUs (AN4838).

Level 1 cache on STM32F7 Series and STM32H7 Series

AN4839

Application note

AN4839 - Rev 2 - March 2018

For further information contact your local STMicroelectronics sales office.