
1 Summary of device errata
The following table gives a quick reference to the STM32L15xxE STM32L15xVD-X STM32L162xE
STM32L162xVD-X device limitations and their status:
A = limitation present, workaround available
N = limitation present, no workaround available
P = limitation present, partial workaround available
“-” = limitation absent
Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround
may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the
rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on
the device or in only a subset of operating modes, of the function concerned.
Table 3. Summary of device limitations
Function
Section Limitation
Status
Rev.
A
Rev.
1,Z
Core
2.1.1
Cortex
®
-M3 LDRD with base in list may result in incorrect base register
when interrupted or faulted
A A
2.1.2
Cortex
®
-M3 event register is not set by interrupts and debug
A A
2.1.3 Interrupted loads to SP can cause erroneous behavior A A
2.1.4 SVC and BusFault/MemManage may occur out of order A A
System
2.2.1
Unexpected system reset when waking up from Stop mode with regulator
in low-power mode
A -
2.2.2
Read protection: a mass erase occurs if the RDP register is written with
level 0 when level 0 is already set
A A
2.2.3
Wake-up sequence from Standby mode fails when using more than one
wake-up source
A A
2.2.4
Erase/program operations partially executed if used multi-cycle STRD
instruction is interrupted
A A
2.2.5
Flash memory wake-up issue when waking up from Stop or Sleep with
flash memory in power-down mode
A -
2.2.6 Delay after enabling an RCC peripheral clock A A
2.2.7 Data EEPROM cycling limited to 100 kcycles N N
2.2.8 LSE crystal oscillator may be disturbed by transitions on PC13 N N
GPIO
2.3.1
If debugger is connected in JTAG mode and JNTRST (PB4) pin
configuration is changed, the connection is lost
A A
2.3.2 Analog switch missing on PC10 GPIO N N
DMA 2.4.1
DMA disable failure and error flag omission upon simultaneous transfer
error and global flag clear
A A
DAC
2.5.1 DMA request not automatically cleared by clearing DMAEN A A
2.5.2
DMA underrun flag not set when an internal trigger is detected on the
clock cycle of the DMA request acknowledge
N N
2.5.3 Spurious activation of DAC output buffer (PA4 and PA5) A A
LCD 2.6.1 Injection from LCD_SEG2, LCD_SEG5 pins A A
TIM
2.7.1
PWM re-enabled in automatic output enable mode despite of system
break
P P
2.7.3 Consecutive compare event missed in specific conditions N N
STM32L15xxE STM32L15xVD-X STM32L162xE STM32L162xVD-X
Summary of device errata
ES0242 - Rev 7
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