Applicability
This document applies to the part numbers of STM32L496xx/4A6xx devices and the device variants as stated in this page.
It gives a summary and a description of the device errata, with respect to the device datasheet and reference manual RM351.
Deviation of the real device behavior from the intended device behavior is considered to be a device limitation. Deviation of the
description in the reference manual or the datasheet from the intended device behavior is considered to be a documentation
erratum. The term “errata” applies both to limitations and documentation errata.
Table 1. Device summary
Reference Part numbers
STM32L496xx
STM32L496AE, STM32L496AG, STM32L496QE, STM32L496QG, STM32L496RE,
STM32L496RG, STM32L496VE, STM32L496VG, STM32L496WG, STM32L496ZE,
STM32L496ZG
STM32L4A6xx STM32L4A6AG, STM32L4A6QG, STM32L4A6RG, STM32L4A6VG, STM32L4A6ZG
Table 2. Device variants
Reference
Silicon revision codes
Device marking
(1)
REV_ID
(2)
STM32L496xx/4A6xx B 0x2000
1. Refer to the device datasheet for how to identify this code on different types of package.
2. REV_ID[15:0] bitfield of DBGMCU_IDCODE register.
STM32L496xx/4A6xx device errata
STM32L496xx STM32L4A6xx
Errata sheet
ES0335 - Rev 19 - December 2024
For further information contact your local STMicroelectronics sales office.
www.st.com
1 Summary of device errata
The following table gives a quick reference to the STM32L496xx/4A6xx device limitations and their status:
A = limitation present, workaround available
N = limitation present, no workaround available
P = limitation present, partial workaround available
“-” = limitation absent
Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround
may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the
rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on
the device or in only a subset of operating modes, of the function concerned.
Table 3. Summary of device limitations
Function Section Limitation
Status
Rev. B
Core
2.1.1 Interrupted loads to SP can cause erroneous behavior A
2.1.2
VDIV or VSQRT instructions might not complete correctly when very short ISRs
are used
A
2.1.3
Store immediate overlapping exception return operation might vector to
incorrect interrupt
A
System
2.2.1
PCPROP area within a single flash memory page becomes unprotected at RDP
change from Level 1 to Level 0
A
2.2.2 MSI frequency overshoot upon Stop mode exit A
2.2.3
Internal voltage reference corrupted upon Stop mode entry with temperature
sensing enabled
A
2.2.4 Spurious brown-out reset after short run sequence A
2.2.5 Full JTAG configuration without NJTRST pin cannot be used A
2.2.6
Current injection from V
DD
to V
DDA
through analog switch voltage booster
A
2.2.7
Both GPIOI and GPIOH pull-up or pull-down activation is done through
PWR_PUCRH or PWR_PDCRH registers
P
2.2.8
Dual-bank boot not working when the boot in flash memory is selected by
BOOT0 pin
A
2.2.9 Dual-bank boot fails with stack pointer placed within aliased SRAM2 A
2.2.10 Unstable LSI when it clocks RTC or CSS on LSE P
2.2.11
FLASH_ECCR corrupted upon reset or power‑down occurring during flash
memory program or erase operation
A
2.2.12 LSE crystal oscillator may be disturbed by transitions on PC13 N
2.2.13 SRAM write error A
2.2.14
Corrupted content of the backup domain due to a missed power-on reset after
this domain supply voltage drop
A
2.2.15 Data cache might be corrupted during flash memory read-while-write operation A
2.2.16
V
DDA
overconsumption under specific condition on PA3 or PB0
N
FW
2.3.1 Code segment unprotected if non-volatile data segment length is zero A
2.3.2 Code and non-volatile data unprotected upon bank swap A
DMA 2.4.1
DMA disable failure and error flag omission upon simultaneous transfer error
and global flag clear
A
FMC
2.5.1 Dummy read cycles inserted when reading synchronous memories N
STM32L496xx STM32L4A6xx
Summary of device errata
ES0335 - Rev 19
page 2/53
