March 2022 ES0231 Rev 6 1/25

STM32F302xB/C

Errata sheet

STM32F302xB/C device limitations

Applicability

This document applies to the part numbers of STM32F302xB/C devices and the device

variants as stated in this page.

It gives a summary and a description of the device errata, with respect to the device

datasheet and reference manual RM0316.

Deviation of the real device behavior from the intended device behavior is considered to be

a device limitation. Deviation of the description in the reference manual or the datasheet

from the intended device behavior is considered to be a documentation erratum. The term

“errata” applies both to limitations and documentation errata.

Table 1. Device summary

Reference Part numbers

STM32F302xB/C

STM32F302CB, STM32F302RB, STM32F302VB,

STM32F302CC, STM32F302RC, STM32F302VC

Table 2. Device variants

Reference

Silicon revision codes

Device marking

(1)

1. Refer to the device data sheet for how to identify this code on different types of package.

REV_ID

(2)

2. REV_ID[15:0] bit field of DBGMCU_IDCODE register. Refer to the reference manual.

STM32F302xB/C

Z 0x1001

Y and 1 0x1003

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Contents STM32F302xB/C

2/25 ES0231 Rev 6

Contents

1 Summary of device errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Description of device errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1.1 Cortex

-M4 with FPU interrupted loads to stack pointer can

cause erroneous behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1.2 VDIV or VSQRT instructions might not complete correctly

when very short ISRs are used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.1 SYSCFG_CFGR2, comparators and operational amplifiers

control registers reset by APB2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.2 Data Read when the CPU accesses successively SRAM address “A”

and SRAM address “A + offset of 16 KBytes (0x4000)” . . . . . . . . . . . . . . 9

2.2.3 Wakeup sequence from Standby mode when using more than one

wakeup source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.4 Full JTAG configuration without NJTRST pin cannot be used . . . . . . . . 10

2.3 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.1 DMA Overrun in dual interleaved mode with single DMA channel . . . . . 10

2.3.2 Sampling time shortened in JAUTO autodelayed mode . . . . . . . . . . . . 10

2.3.3 Injected queue of context is not available in case of JQM = 0 . . . . . . . . 11

2.3.4 Load multiple not supported by ADC interface . . . . . . . . . . . . . . . . . . . 11

2.3.5 ADEN bit cannot be set immediately after the ADC calibration is done . 11

2.3.6 Overrun flag might not be set when the converted data have not been

read before new data are written . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.7 ADC differential mode common mode input range . . . . . . . . . . . . . . . . 12

2.3.8 Imprecise V

REFINT

calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4.1 Packing mode limitation at reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4.2 SPI CRC may be corrupted when a peripheral connected to the same

DMA channel of the SPI is under DMA transaction near the end of

transfer or end of transfer ‘-1’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.4.3 BSY bit may stay high at the end of a SPI data transfer in slave mode . 14

2.4.4 Last data bit or CRC calculation may be corrupted for the data received

in SPI/I2S master mode depending on the feedback communication

clock timing with respect to the APB clock . . . . . . . . . . . . . . . . . . . . . . . 15

2.5 I

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15