February 2016 DocID026182 Rev 4 1/24
1
STM32L063x8
Errata sheet
STM32L063x8 device limitations
Silicon identification
This errata sheet applies to the revision A, Z, Y and X of STMicroelectronics STM32L063x8
microcontrollers.
The STM32L063x8 devices feature an ARM
®
32-bit Cortex
®
-M0+ core.
The full list of part numbers is shown in Table 2. The products can be identified as shown in
Table 1:
by the revision code marked below the order code on the device package
by the last three digits of the Internal order code printed on the box label
Table 1. Device identification
(1)
1. The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device (see the
STM32L0x3 reference manual for details on how to find the revision code).
Order code Revision code marked on device
(2)
2. Refer to the device datasheet for details on how to identify the revision code and the date code on the
different packages.
STM32L063x8 “A”, “Z”, “Y”, “X”
Table 2. Device summary
Reference Part number
STM32L063x8 STM32L063C8, STM32L063R8
www.st.com
Contents STM32L063x8
2/24 DocID026182 Rev 4
Contents
1 ARM 32-bit Cortex-M0+ limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 STM32L063x8 silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 Writing in byte mode to the GPIOx_OTYPER register does not work . . . 8
2.1.2 Exiting Stop mode on a reset event is not possible when HSI16 is
the clock system and it is selected as wakeup clock . . . . . . . . . . . . . . . . 8
2.1.3 Protection level1 does not work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.4 LSE bypass feature cannot be used in Standby mode . . . . . . . . . . . . . . 9
2.1.5 PA4 and PA5 cannot be redirected to comparator 2 minus input . . . . . 10
2.1.6 PB14 output speed configuration interferes with PB13 . . . . . . . . . . . . . 10
2.1.7 ADC transfer curve issue at VREF+/2 when VREF+ < VDDA . . . . . . . . 11
2.1.8 Delay after an RCC peripheral clock enabling . . . . . . . . . . . . . . . . . . . . 11
2.1.9 PB6 and PB7 AF1 alternate functions not available when
LCD controller is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.10 Flash memory wakeup issue when waking up from Stop or Sleep
with Flash in power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.11 Unexpected system reset when waking up from Stop mode with
regulator in low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.12 I2C and USART cannot wake up the device from Stop mode . . . . . . . . 13
2.1.13 LDM, STM, PUSH and POP not allowed in IOPORT bus . . . . . . . . . . . 14
2.1.14 BOOT_MODE bits do not reflect the selected boot mode . . . . . . . . . . . 14
2.2 ADC peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 Incorrect first ADC conversion result when delay between
two consecutive conversions is too long . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.2 Overrun flag might not be set when converted data have not been read
before new data are written . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 Comparator limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.1 COMP1_CSR and COMP2_CSR lock bit reset by SYSCFGRST bit
in RCC_APB2RSTR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.2 Output of comparator 2 cannot be internally connected to input 1
of low-power timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 RTC limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.1 Spurious tamper detection when disabling the tamper channel . . . . . . . 16
2.4.2 Detection of a tamper event occurring before enabling the tamper
detection is not supported in edge detection mode . . . . . . . . . . . . . . . . 16
