October 2017 Doc ID14400 Rev 6 1/260
1
RM0013
Reference manual
STM8L001xx and STM8L101xx microcontroller families
Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM8L001xx and STM8L101xx microcontrollers memory and peripherals.
The STM8L is a family of microcontrollers with different memory densities, packages and
peripherals. The STM8L is designed for low-power applications.
For ordering information, pin description, mechanical and electrical device characteristics,
refer to the STM8L datasheets.
For information on the STM8 SWIM communication protocol and debug module, refer to the
user manual UM0470.
For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).
www.st.com
Contents RM0013
2/260 Doc ID14400 Rev 6
Contents
1 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1 Register description abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1 CPU introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.1 Description of CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.2 STM8 CPU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3 Global configuration register (CFG_GCR) . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.1 Activation level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.2 SWIM disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.3 Description of global configuration register (CFG_GCR) . . . . . . . . . . . . 23
2.3.4 Global configuration register map and reset values . . . . . . . . . . . . . . . 23
3 Single wire interface module (SWIM) and debug module (DM) . . . . . 24
3.1 SWIM and DM introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2 SWIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3 SWIM modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4 Debug module (DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4 Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . 26
4.1 Flash and EEPROM introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 Flash and EEPROM glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3 Main Flash memory features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4.1 User boot area (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4.2 Data EEPROM (DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4.3 Main program area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.4.4 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5.2 Memory access security system (MASS) . . . . . . . . . . . . . . . . . . . . . . . 29
4.6 Memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
