Introduction
High performance STM32 microcontrollers and release constraints on software architecture open the door to more advanced
software solutions. Advanced software applications require independent components to run simultaneously. Microcontrollers of
the STM32H745/755 and STM32H747/757 lines feature an asymmetric dual-core architecture; thus, processing parallelism is
guaranteed with two CPUs capable of running different payloads. Nevertheless, there are often tasks that need to communicate
with one another to share information and ensure correct processing. For these reasons, the inter-processor communication
(IPC) layers are needed to link data dependent tasks.
To ease core-to-core interactions and reduce time to market, STM32CubeH7 propose a set of standard middleware
that implement the inter-processor communication channel (IPCC) between the Arm
®
Cortex
®
-M7 and Arm
®
Cortex
®
-M4.
This application note provides an overview of the dual-core communication technique. It introduces the inter-processor
communication channels such as OpenAMP, RPMsg, FreeRTOS
™
as well as the message buffer and custom communication
mechanism. It also provides a detailed flowchart with snippet code example to describe how to use OpenAMP and FreeRTOS
™
to create a communication channel between cores.
STM32H745/755 and STM32H747/757 lines inter-processor communications
AN5617
Application note
AN5617 - Rev 1 - February 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1 General information
This document applies to STM32H745/755 and STM32H747/757 lines Arm
®
-based devices.
Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
The following table present a non-exhaustive list of terms and acronyms used in this document.
Table 1. Terms and accronyms
Term or acronym Definition
AMP Asymmetric multi-processing
API Application programming interface
AXISRAM Advanced extensible interface SRAM
BKSRAM Backup SRAM
CMSIS
Cortex
®
microcontroller software interface standard
CPU Central processing unit
DTCM Data tightly coupled memory
EXTI External interrupt
FreeRTOS Free real-time operating system
HSEM Hardware semaphore free interrupt
IPC Inter-processor communication
IPCC Inter-processor communication channel
ITCM Instruction tightly coupled memory
MDMA Master direct memory access
MPU Memory protection unit
MW Middleware
NVIC Nested vectored interrupt controller
OpenAMP Open asymmetric multi-processing
RPMsg Remote processor messaging
RTOS Real-time operating system
SEV Send-event instruction
SRAM Static random access memory
TCM Tightly moupled memory
TXEV Transmit event
AN5617
General information
AN5617 - Rev 1
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