February 2016 DocID027207 Rev 4 1/21
1
STM32L082KB/Z
Errata sheet
STM32L082KB/Z device limitations
Silicon identification
This errata sheet applies to the revision A, B and Z of STMicroelectronics STM32L082KB/Z
microcontrollers.
The STM32L082KB/Z devices feature an ARM
®
32-bit Cortex
®
-M0+ core.
The full list of part numbers is shown in Table 2. The products can be identified as shown in
Table 1:
• by the revision code marked below the order code on the device package
• by the last three digits of the Internal order code printed on the box label
Table 1. Device identification
(1)
1. The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device (see the
STM32L0x2 reference manual for details on how to find the revision code).
Order code Revision code marked on device
(2)
2. Refer to the device datasheet for details on how to identify the revision code and the date code on the
different packages.
STM32L082KB/Z “A” (engineering samples), “B” and “Z”
Table 2. Device summary
Reference Part number
STM32L082KB/Z STM32L082KB, STM32L082KZ
www.st.com
Contents STM32L082KB/Z
2/21 DocID027207 Rev 4
Contents
1 ARM 32-bit Cortex-M0+ limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 STM32L073x8/B/Z silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 Delay after an RCC peripheral clock enabling . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 BFB2 bit does not select boot from Bank 2 system memory . . . . . . . . . . 8
2.1.3 PE2 AF2 alternate function (TIM3_ETR) not available . . . . . . . . . . . . . 10
2.1.4 PB6, PB7, PD0, PD1, PD7 AF1 alternate functions not available when
LCD controller is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.5 Flash memory wakeup issue when waking up from Stop or Sleep
with Flash in power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.6 Unexpected system reset when waking up from Stop mode with
regulator in low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.7 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.8 I2C and USART cannot wake up the device from Stop mode . . . . . . . . 12
2.1.9 LDM, STM, PUSH and POP not allowed in IOPORT bus . . . . . . . . . . . 13
2.1.10 BOOT_MODE bits do not reflect the selected boot mode . . . . . . . . . . . 13
2.2 Comparator limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1 COMP1_CSR and COMP2_CSR lock bit reset by SYSCFGRST bit
in RCC_APB2RSTR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.2 Output of comparator 2 cannot be internally connected to input 1
of low-power timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 RTC limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1 Spurious tamper detection when disabling the tamper channel . . . . . . . 14
2.3.2 Detection of a tamper event occurring before enabling the tamper
detection is not supported in edge detection mode . . . . . . . . . . . . . . . . 14
2.4 I
2
C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.1 Wrong behaviors in Stop mode when waking up from Stop mode is
disabled in I
2
C peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.2 Wrong data sampling when data set-up time (t
SU;DAT
) is smaller than
one I2CCLK period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5 SPI/I2S peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5.1 In I2S slave mode, WS level must to be set by the external master
when enabling the I2S peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5.2 BSY bit may stay high at the end of a SPI data transfer in slave mode . 16
