Applicability
This document applies to the part numbers of STM32F412xE and STM32F412xG devices and the device variants as stated in
this page.
It gives a summary and a description of the device errata, with respect to the device datasheet and reference manual RM0402.
Deviation of the real device behavior from the intended device behavior is considered to be a device limitation. Deviation of the
description in the reference manual or the datasheet from the intended device behavior is considered to be a documentation
erratum. The term
“errata” applies both to limitations and documentation errata.
Table 1. Device summary
Reference Part numbers
STM32F412xx
STM32F412CE, STM32F412CG, STM32F412GDIE, STM32F412RE, STM32F412RG, STM32F412VE,
STM32F412VG, STM32F412ZE, STM32F412ZG
Table 2. Device variants
Reference
Silicon revision codes
Device marking
(1)
REV_ID
(2)
STM32F412xx
Z 0x1001
B 0x2000
1
0x3000
C
1. Refer to the device datasheet for how to identify this code on different types of package.
2. REV_ID[15:0] bitfield of DBGMCU_IDCODE register.
STM32F412xE and STM32F412xG device errata
STM32F412xE and STM32F412xG
Errata sheet
ES0305 - Rev 13 - January 2024
For further information contact your local STMicroelectronics sales office.
www.st.com
1 Summary of device errata
The following table gives a quick reference to the STM32F412xE and STM32F412xG device limitations and their
status:
A = limitation present, workaround available
N = limitation present, no workaround available
P = limitation present, partial workaround available
“-” = limitation absent
Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround
may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the
rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on
the device or in only a subset of operating modes, of the function concerned.
Table 3. Summary of device limitations
Function Section Limitation
Status
Rev.
Z
Rev.
B
Rev.
1
Rev.
C
Core
2.1.1 Interrupted loads to SP can cause erroneous behavior
A A A A
2.1.2
VDIV or VSQRT instructions might not complete correctly when
very short ISRs are used
A A A A
2.1.3
Store immediate overlapping exception return operation might
vector to incorrect interrupt
A A A A
System
2.2.1 Debugging Stop mode and SysTick timer A A A A
2.2.2 Debugging Stop mode with WFE entry A A A A
2.2.3 Debugging Sleep/Stop mode with WFE/WFI entry A A A A
2.2.4
Wake-up sequence from Standby mode when using more than
one wake-up source
A A A A
2.2.5 Full JTAG configuration without NJTRST pin cannot be used A A A A
2.2.6 MPU attribute to RTC and IWDG registers incorrectly managed A A A A
2.2.7 Delay after an RCC peripheral clock enabling A A A A
2.2.8 Internal noise impacting the ADC accuracy A A A A
2.2.9
Possible delay in backup domain protection disabling/enabling
after programming the DBP bit
A A A A
2.2.10 PC13 signal transitions disturb LSE N N N N
2.2.11
In some specific cases, DMA2 data corruption occurs when
managing AHB and APB2 peripherals in a concurrent way
A A A A
2.2.12 Flash sector erase issue for sectors 5 to 11 A - - -
FSMC
2.3.1
Dummy read cycles inserted when reading synchronous
memories
N N N N
2.3.2 Wrong data read from a busy NAND memory A A A A
2.3.3 Spurious clock stoppage with continuous clock feature enabled A A A A
2.3.4 Data read might be corrupted when the write FIFO is disabled A A A A
QUADSPI
2.4.1 First nibble of data not written after dummy phase A A A A
2.4.2
Wrong data from memory-mapped read after an indirect mode
operation
A A A A
2.4.3
Memory-mapped read operations may fail when timeout counter
is enabled
P P P P
STM32F412xE and STM32F412xG
Summary of device errata
ES0305 - Rev 13
page 2/37
