STM32U5

DMA: Input/Ouput LLI control

Rev 1.0

Hello, and welcome to this presentation which describes

the control of the input and output signals of the GPDMA

and LPDMA channels.

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• Flexible intra/inter channel synchronization at LLI level

• Programmable input control

• Data (block, 2D block) or LLI or channel

• Transfer complete hardware signal generation

• Possibly used as trigger input of another channel

• No need to be cleared, unlike the flag

DMA transfer & input/output control

DMA_CxTR2

The DMA_CxTR2 register defines the input control

(request, trigger events) and the output control (transfer

complete event) of the transfer handled by the channel x

at the LLI level.

This enables a flexible event-driven and hardware-based

scheduling of a transfer under the global control of the

software.

In the figure, a timer is used to trigger the transfer of the

data received by the SPI module. When this transfer

completes, a link to LLI2 is performed. The LLI2 handles

an I2C transmission.

When this transfer completes, a link is performed to

restore the settings related to the SPI receive transfer.

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