1 Summary of device errata
The following table gives a quick reference to the STM32L151x6/8/B and STM32L152x6/8/B device limitations
and their status:
A = limitation present, workaround available
N = limitation present, no workaround available
P = limitation present, partial workaround available
“-” = limitation absent
Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround
may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the
rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on
the device or in only a subset of operating modes, of the function concerned.
Table 3. Summary of device limitations
Function
Section Limitation
Status
Rev.
A,Y
Rev.
X
Rev.
W
Rev.
1,V
Core
2.1.1
Cortex
®
-M3 LDRD with base in list may result in incorrect base
register when interrupted or faulted
A A A A
2.1.2
Cortex
®
-M3 event register is not set by interrupts and debug
A A A A
2.1.3 Interrupted loads to SP can cause erroneous behavior A A A A
2.1.4 SVC and BusFault/MemManage may occur out of order A A A A
System
2.2.1 Bootloader unavailability N - - -
2.2.2 Undefined instruction exception during IAP A - - -
2.2.3 Factory-trimming values not available A A A -
2.2.4 Operating temperature range limited to –10 °C to +85 °C N N - -
2.2.6
Unexpected system reset when waking up from Stop mode with
regulator in low-power mode
A A A A
2.2.8
Unexpected flash/EEPROM behavior on system reset during
programming/erasing
N - - -
2.2.9
Flash memory wake-up issue when waking up from Stop or Sleep
with flash memory in power-down mode
A A A A
2.2.10
MCU may not restart after a reset when using HSE bypass as
main clock source
N N - -
2.2.11 HSEBYP bit of clock control register has an undefined reset value - - A A
2.2.12 Delay after enabling an RCC peripheral clock A A A A
2.2.13
Debug support for low-power modes with entry through the WFE
instruction
A A A A
2.2.14 LSE crystal oscillator may be disturbed by transitions on PC13 N N N N
GPIO 2.3.1 Pull-up on PB7 when configured in analog mode A A A A
DMA 2.4.1
DMA disable failure and error flag omission upon simultaneous
transfer error and global flag clear
A A A A
ADC 2.5.1 ADC converter partially tested on parts with date code before 047 N - - -
DAC
2.6.1 DMA request not automatically cleared by clearing DMAEN A A A A
2.6.2
DMA underrun flag not set when an internal trigger is detected on
the clock cycle of the DMA request acknowledge
N N N N
2.6.3 Spurious activation of DAC output buffer (PA4 and PA5) A A A A
STM32L151x6/8/B STM32L152x6/8/B
Summary of device errata
ES0125 - Rev 16
page 2/36