January 2024 RM0434 Rev 13 1/1530
1
RM0434
Reference manual
Multiprotocol wireless 32-bit MCU Arm
®
-based Cortex
®
-M4 with
FPU, Bluetooth
®
Low-Energy and 802.15.4 radio solution
Introduction
This document is addressed to application developers. It provides complete information on
how to use the STM32WB55xx and STM32WB35xx microcontrollers.
These multiprotocol wireless and ultra-low-power devices embed a powerful
ultra-low-power radio compliant with the Bluetooth
®
Low Energy SIG specification 5.4 and
with IEEE 802.15.4-2011. They contain a dedicated Arm
®
Cortex
®
-M0+ for performing the
real-time low layer operation.
The STM32WB55xx and STM32WB35xx microcontrollers feature different memory sizes,
packages and peripherals, and include ST state of the art patented technology.
Related documents
Available from STMicroelectronics web site www.st.com:
STM32WB55xx and STM32WB35xx datasheets
STM32WB55xx and STM32WB35xx errata sheets
For information on the Arm
®
Cortex
®
-M4 and Cortex
®
-M0+ cores, refer, respectively, to the
corresponding Technical Reference Manuals, available from the www.arm.com website.
For information on 802.15.4 refer to the IEEE website (www.ieee.org).
For information on Bluetooth
®
refer to www.bluetooth.com.
www.st.com
Contents RM0434
2/1530 RM0434 Rev 13
Contents
1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
1.1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
1.2 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
1.3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1.4 Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2 System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.1.1 S0: CPU1 (CPU1 Cortex
®
-M4) I-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.1.2 S1: CPU1 (CPU1 Cortex
®
-M4) D-bus . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.1.3 S2: CPU1 (CPU1 Cortex
®
-M4) S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.1.4 S3: CPU2 (Cortex®-M0+) S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.1.5 S4, S5: DMA-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.1.6 S6: Radio system-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.1.7 BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.2.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 67
2.2.3 Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.3 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.4 CPU2 boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.5 CPU2 SRAM fetch disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3 Embedded flash memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.2 FLASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.3 FLASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.3.1 Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.3.2 Empty check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.3.3 Error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.3.4 Read access latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.3.5 Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . 80
3.3.6 Flash memory program and erase operations . . . . . . . . . . . . . . . . . . . . 83
