November 2016 DocID028471 Rev 4 1/17

STM32L011x3/4

Errata sheet

STM32L011x3/4 device limitations

Silicon identification

This errata sheet applies to the revision ‘A’ and ‘Z’ of STMicroelectronics STM32L011x3/4

microcontrollers.

The STM32L011x3/4 devices feature an ARM

32-bit Cortex

-M0+ core.

The full list of part numbers is shown in Table 2. The products can be identified as shown in

Table 1:

• by the revision code marked below the order code on the device package

• by the last three digits of the Internal order code printed on the box label

Table 1. Device identification

(1)

1. The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device (see the

STM32L0x1 reference manual for details on how to find the revision code).

Order code Revision code marked on device

(2)

2. Refer to the device datasheet for details on how to identify the revision code and the date code on the

different packages.

STM32L011x3/4 ‘A’ and ‘Z’

Table 2. Device summary

Reference Part number

STM32L011x3/4

STM32L011G3, STM32L011K3, STM32L011E3, STM32L011F3, STM32L011D3,

STM32L011G4, STM32L011K4, STM32L011E4, STM32L011F4, STM32L011D4

www.st.com

Contents STM32L011x3/4

2/17 DocID028471 Rev 4

Contents

1 ARM 32-bit Cortex-M0+ limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 STM32L011x3/4 silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1.1 Delay after an RCC peripheral clock enabling . . . . . . . . . . . . . . . . . . . . . 7

2.1.2 I2C and USART cannot wake up the device from Stop mode . . . . . . . . . 7

2.1.3 LDM, STM, PUSH and POP not allowed in IOPORT bus . . . . . . . . . . . . 8

2.1.4 BOOT_MODE bits do not reflect the selected boot mode . . . . . . . . . . . . 8

2.1.5 NSS pin synchronization required when using bootloader

with SPI1 interface on TSSOP14 package . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 ADC limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.1 Overrun flag might not be set when converted data have not been read

before new data are written . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Comparator limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3.1 COMP1_CSR and COMP2_CSR lock bit reset by SYSCFGRST bit

in RCC_APB2RSTR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 RTC limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4.1 Detection of a tamper event occurring before enabling the tamper

detection is not supported in edge detection mode . . . . . . . . . . . . . . . . . 9

2.5 I

C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.5.1 Wrong behaviors in Stop mode when waking up from Stop mode is

disabled in I

C peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.5.2 Wrong data sampling when data set-up time (t

SU;DAT

) is smaller than

one I2CCLK period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.5.3 10-bit master Master mode: new transfer cannot be launched if first

part of the address has not been acknowledged by the slave . . . . . . . . 11

2.6 SPI peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.6.1 BSY bit may stay high at the end of a SPI data transfer in Slave mode 11

2.6.2 Corrupted last bit of data and/or CRC, received in Master mode with

delayed SCK feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.6.3 Wrong CRC transmitted in Master mode with delayed SCK feedback . 13

2.7 USART limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.7.1 nRTS is active while RE or UE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.7.2 DMA channel 3 (CH3) not functional when USART2_RX used for

data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.8 LPUART limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14