February 2017 DocID027643 Rev 4 1/56
1
AN4667
Application note
STM32F7 Series system architecture and performance
Introduction
The STM32F7 Series devices are the first ARM
®
Cortex
®
-M7 based 32-bit microcontrollers.
Taking advantage of ST’s ART accelerator
™
as well as an L1-cache, the STM32F7 Series
devices deliver the maximum theoretical performance of the Cortex
®
-M7.
The benchmark scores steadily reach 1082 CoreMark and 462 DMIPS, whether the code is
executed from the embedded Flash memory, from the internal RAMs or from the external
memories (SRAM, SDRAM or Quad-SPI Flash memory).
The STM32F7 Series devices bring a high level of performance thanks to:
• A powerful superscalar pipeline and DSP capabilities providing a fast real time response
with a low interrupt latency
• An efficient access to the large external memories
• A high performance floating point capability for complex calculations
This application note presents the STM32F7 global architecture as well as the memory
interfaces and features which provide a high flexibility to achieve the best performance and
additional code and data sizes. It also presents the multi-master architecture that
contributes to the system performance and offloads the CPU.
The application note also provides a software demonstration of the architecture
performance of the STM32F7 Series devices in various memory partitioning configurations
(different code and data locations) as well as the performance of architecture where DMAs
are enabled.
This application note is provided with the X-CUBE-32F7PERF embedded software package
that includes two projects:
• Stm32f7_performances project aims to demonstrate the performance of the STM32F7
architecture in different configurations, that is, the execution of the code and the data
storage in different memory locations using ART accelerator
™
and caches.
• Stm32f7_performances_DMAs aims to demonstrate the performance of the architecture
in multi-master configuration.
Each project is done for the following available boards: STM32756G-EVAL, STM32F769I-
EVAL and STM32F723E-DISCO boards.
www.st.com
Contents AN4667
2/56 DocID027643 Rev 4
Contents
1 STM32F7 Series system architecture overview . . . . . . . . . . . . . . . . . . . 6
1.1 Cortex
®
-M7 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Cortex
®
-M7 system caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Cortex
®
-M7 bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.1 AXI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.2 TCM bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.3 AHBS bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.4 AHBP bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 STM32F7 bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5 STM32F7 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.5.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5.3 External memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.6 DMAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.7 Main differences between the STM32F7 Series devices from
architecture point of view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1 FFT demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2 Project configuration of the CPU memory access demonstration . . . . . . 22
2.3 Project configuration of the CPU memory access with
DMA activation demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.1 Step 1: configure the different DMA parameters . . . . . . . . . . . . . . . . . . 27
2.3.2 Step 2: check the configuration and the DMA transfer(s) . . . . . . . . . . . 30
2.3.3 Step 3: get the results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3 Results and analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1 CPU memory access performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2 CPU memory access performance with DMA usage . . . . . . . . . . . . . . . . 38
4 Performance ranking and comparison inside the
STM32F7 Series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.1 Performance ranking inside the STM32F7 Series . . . . . . . . . . . . . . . . . . 46
4.2 Guideline to select an STM32F7 device . . . . . . . . . . . . . . . . . . . . . . . . . . 48
