Applicability

This document applies to the part numbers of STM32C071x8/xB devices and the device variants as stated in this page.

It gives a summary and a description of the device errata, with respect to the device datasheet and reference manual RM0490.

Deviation of the real device behavior from the intended device behavior is considered to be a device limitation. Deviation of the

description in the reference manual or the datasheet from the intended device behavior is considered to be a documentation

erratum. The term “errata” applies both to limitations and documentation errata.

Table 1. Device summary

Reference Part numbers

STM32C071xx

STM32C071F8, STM32C071G8, STM32C071K8, STM32C071C8, STM32C071R8, STM32C071FB,

STM32C071GB, STM32C071KB, STM32C071CB, STM32C071RB

Table 2. Device variants

Reference

Silicon revision codes

Device marking

(1)

REV_ID

(2)

STM32C071xx Z 0x1001

1. Refer to the device datasheet for how to identify this code on different types of package.

2. REV_ID[15:0] bitfield of DBGMCU_IDCODE register.

STM32C071x8/xB device errata

STM32C071x8/xB

Errata sheet

ES0618 - Rev 1 - August 2024

For further information contact your local STMicroelectronics sales office.

www.st.com

1 Summary of device errata

The following table gives a quick reference to the STM32C071x8/xB device limitations and their status:

A = limitation present, workaround available

N = limitation present, no workaround available

P = limitation present, partial workaround available

“-” = limitation absent

Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround

may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the

rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on

the device or in only a subset of operating modes, of the function concerned.

Table 3. Summary of device limitations

Function Section Limitation

Status

Rev. Z

System 2.2.1 LSE crystal oscillator may be disturbed by transitions on PC13 N

DMA 2.3.1

DMA disable failure and error flag omission upon simultaneous transfer error

and global flag clear

DMAMUX

2.4.1 SOFx not asserted when writing into DMAMUX_CFR register N

2.4.2 OFx not asserted for trigger event coinciding with last DMAMUX request N

2.4.3 OFx not asserted when writing into DMAMUX_RGCFR register N

2.4.4

Wrong input DMA request routed upon specific DMAMUX_CxCR register write

coinciding with synchronization event

ADC 2.5.1 Overrun flag is not set if EOC reset coincides with new conversion end P

TIM

2.6.1

One-pulse mode trigger not detected in master-slave reset + trigger

configuration

2.6.2 Consecutive compare event missed in specific conditions N

2.6.3 Output compare clear not working with external counter reset P

2.6.4 Bidirectional break mode not working with short pulses N

RTC

2.7.1 Calendar initialization may fail in case of consecutive INIT mode entry A

2.7.2 Alarm flag may be repeatedly set when the core is stopped in debug N

I2C

2.8.1

Wrong data sampling when data setup time (t

SU;DAT

) is shorter than one I2C

kernel clock period

2.8.2 Spurious bus error detection in master mode A

2.8.3 OVR flag not set in underrun condition N

2.8.4 Transmission stalled after first byte transfer A

2.8.5 SDA held low upon SMBus timeout expiry in slave mode A

USART

2.9.1 Anticipated end-of-transmission signaling in SPI slave mode A

2.9.2 Data corruption due to noisy receive line A

2.9.3 Received data may be corrupted upon clearing the ABREN bit A

2.9.4 Noise error flag set while ONEBIT is set N

SPI/I2S

2.10.1 BSY bit may stay high when SPI is disabled A

2.10.2 BSY bit may stay high at the end of data transfer in slave mode A

USB 2.11.1 Buffer description table update completes after CTR interrupt triggers A

STM32C071x8/xB

Summary of device errata

ES0618 - Rev 1

page 2/16