Applicability
This document applies to the part numbers of STM32F401xB/xC devices and the device variants as stated in this page.
It gives a summary and a description of the device errata, with respect to the device datasheet and reference manual RM0368.
Deviation of the real device behavior from the intended device behavior is considered to be a device limitation. Deviation of the
description in the reference manual or the datasheet from the intended device behavior is considered to be a documentation
erratum. The term “errata” applies both to limitations and documentation errata.
Table 1. Device summary
Reference Part numbers
STM32F401xB STM32F401VB, STM32F401RB, STM32F401CB
STM32F401xC STM32F401VC, STM32F401RC, STM32F401CC
Table 2. Device variants
Reference
Silicon revision codes
Device marking
(1)
REV_ID
(2)
STM32F401xB/xC
A 0x1000
1 0x1001
Z 0x1001
1. Refer to the device datasheet for how to identify this code on different types of package.
2. REV_ID[15:0] bitfield of DBGMCU_IDCODE register.
STM32F401xB and STM32F401xC device errata
STM32F401xB/xC
Errata sheet
ES0222 - Rev 7 - January 2024
For further information contact your local STMicroelectronics sales office.
www.st.com
1 Summary of device errata
The following table gives a quick reference to the STM32F401xB/xC device limitations and their status:
A = workaround available
N = no workaround available
P = partial workaround available
Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround
may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the
rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on
the device or in only a subset of operating modes, of the function concerned.
Table 3. Summary of device limitations
Function Section Limitation
Status
Rev.
A
Rev.
1
Rev.
Z
Core
2.1.1 Interrupted loads to SP can cause erroneous behavior
A A A
2.1.2
VDIV or VSQRT instructions might not complete correctly when very
short ISRs are used
A A A
2.1.3
Store immediate overlapping exception return operation might vector
to incorrect interrupt
A A A
System
2.2.1 Debugging Stop mode and SysTick timer A A A
2.2.2 Debugging Stop mode with WFE entry A A A
2.2.3 Debugging Sleep/Stop mode with WFE/WFI entry A A A
2.2.4
Wake-up sequence from Standby mode when using more than one
wake-up source
A A A
2.2.5 Full JTAG configuration without NJTRST pin cannot be used A A A
2.2.6 MPU attribute to RTC and IWDG registers incorrectly managed A A A
2.2.7 Delay after an RCC peripheral clock enabling A A A
2.2.8 Internal noise impacting the ADC accuracy A A A
2.2.9
Possible delay in backup domain protection disabling/enabling after
programming the DBP bit
A A A
2.2.10 PC13 signal transitions disturb LSE N N N
2.2.11
PB5 I/O V
IN
limitation
A A A
2.2.12
PA0 I/O V
IN
limitation in Standby mode
A A A
2.2.13 PH1 cannot be used as a GPIO in HSE bypass mode N N N
2.2.14
Extra power consumption may be observed on the UQFN48, LQFP64
and LQPF100 packages
A A A
2.2.15
In some specific cases, DMA2 data corruption occurs when managing
AHB and APB2 peripherals in a concurrent way
A A A
ADC 2.3.1 ADC sequencer modification during conversion A A A
DAC
2.4.1 DMA request not automatically cleared by clearing DMAEN A A A
2.4.2
DMA underrun flag not set when an internal trigger is detected on the
clock cycle of the DMA request acknowledge
N N N
TIM
2.5.1
PWM re-enabled in automatic output enable mode despite of system
break
P P P
2.5.3 Consecutive compare event missed in specific conditions N N N
2.5.4 Output compare clear not working with external counter reset P P P
STM32F401xB/xC
Summary of device errata
ES0222 - Rev 7
page 2/33
