DMA Direct Memory Transfer
DMA Features
14 independently configurable channels split to DMA1 & DMA2
Hardware requests or software trigger on each channel.
Software programmable priorities: Very high, High, Medium or Low. (Hardware
priority in case of equality).
Programmable and Independent source and destination transfer data size: Byte,
Halfword or Word.
3 event flags for each channel: DMA Half Transfer, DMA Transfer complete and
DMA Transfer Error.
Memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers and
peripheral-to-peripheral transfers.
Faulty channel is automatically hardware disabled in case of bus access error.
Programmable number of data to be transferred: up to 65535.
Support for circular buffer management.
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