Applicability

This document applies to the part numbers of STM32H742xI/G, STM32H743xI/G, STM32H750xB, STM32H753xI devices and

the device variants as stated in this page.

It gives a summary and a description of the device errata, with respect to the device datasheet and reference manual RM0433.

Deviation of the real device behavior from the intended device behavior is considered to be a device limitation. Deviation of the

description in the reference manual or the datasheet from the intended device behavior is considered to be a documentation

erratum. The term

“errata” applies both to limitations and documentation errata.

Table 1. Device summary

Reference Part numbers

STM32H742xI/G

STM32H742VI, STM32H742ZI, STM32H742II, STM32H742BI, STM32H742XI, STM32H742AI,

STM32H742VG, STM32H742ZG, STM32H742IG, STM32H742BG, STM32H742XG, STM32H742AG

STM32H743xI/G

STM32H743VI, STM32H743ZI, STM32H743II, STM32H743BI, STM32H743XI, STM32H743AI,

STM32H743VG, STM32H743ZG, STM32H743IG, STM32H743BG, STM32H743XG, STM32H743AG

STM32H750xB STM32H750VB, STM32H750IB, STM32H750XB, STM32H750ZB

STM32H753xI STM32H753VI, STM32H753ZI, STM32H753II, STM32H753BI, STM32H753XI, STM32H753AI

Table 2. Device variants

Reference

Silicon revision codes

Device marking

(1)

REV_ID

(2)

STM32H742xI/G, STM32H743xI/G,

STM32H750xB, STM32H753xI

Y, W 0x1003

X 0x2001

V 0x2003

1. Refer to the device datasheet for how to identify this code on different types of package.

2. REV_ID[15:0] bitfield of DBGMCU_IDC register.

STM32H742xI/G, STM32H743xI/G, STM32H750xB, STM32H753xI device errata

STM32H742xI/G, STM32H743xI/G

STM32H750xB, STM32H753xI

Errata sheet

ES0392 - Rev 12 - December 2023

For further information contact your local STMicroelectronics sales office.

www.st.com

1 Summary of device errata

The following table gives a quick reference to the STM32H742xI/G, STM32H743xI/G, STM32H750xB,

STM32H753xI device limitations and their status:

A = limitation present, workaround available

N = limitation present, no workaround available

P = limitation present, partial workaround available

“-” = limitation absent

Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround

may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the

rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on

the device or in only a subset of operating modes, of the function concerned.

Table 3. Summary of device limitations

Function Section Limitation

Status

Rev.

Y,W

Rev.

Arm 32-bit

Cortex-M7 core

2.1.1

Cortex-M7 data corruption when using Data cache configured in

write-through

N N N

2.1.2

Cortex

-M7 FPU interrupt not present on NVIC line 81

N N N

System

2.2.1 Timer system breaks do not work N - -

2.2.2 Clock recovery system synchronization with USB SOF does not work A - -

2.2.3 SysTick external clock is not HCLK/8 A - -

2.2.4 Option byte loading can be done with the user wait-state configuration A - -

2.2.5

Flash memory BusFault address register may not be valid when an

ECC double error occurs

A - -

2.2.6 Flash ECC address register may not be updated N - -

2.2.7 PCROP-protected areas in flash memory may be unprotected A - -

2.2.8

Flash memory bank swapping may impact embedded flash memory

interface behavior

N - -

2.2.9 Reading from AXI SRAM may lead to data read corruption A - -

2.2.10

Clock switching does not work when an LSE failure is detected by

CSS

A - -

2.2.11

RTC stopped when a system reset occurs while the LSI is used as

clock source

A - -

2.2.12 USB OTG_FS PHY drive limited on DP/DM pins N - -

2.2.13

Unexpected leakage current on I/Os when V

higher that V

A - -

2.2.14 LSE oscillator driving capability selection bits are swapped A - -

2.2.15 HRTIM internal synchronization does not work N - -

2.2.16

Device stalled when two consecutive level regressions occur without

accessing from/to backup SRAM

- A A

2.2.17 Invalid flash memory CRC P - -

2.2.18

GPIO assigned to DAC cannot be used in output mode when the

DAC output is connected to on-chip peripheral

N N N

2.2.19 Unstable LSI when it clocks RTC or CSS on LSE P P P

2.2.20 480 MHz maximum CPU frequency not available P - -

2.2.21 VDDLDO is not available on TFBGA100 package N N N

STM32H742xI/G, STM32H743xI/G, STM32H750xB, STM32H753xI

Summary of device errata

ES0392 - Rev 12

page 2/71