
1 Documentation conventions
1.1 General information
For information on the Arm
®
Cortex
®
-M0+ core, refer to the Cortex
®
-M0+ technical reference manual, available
from the www.arm.com website.
For information on Bluetooth
®
refer to www.bluetooth.com website.
Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
1.2
List of abbreviations for registers
The following abbreviations are used in register descriptions:
Table 1. List of abbreviations for registers
read/write (rw or R/W) Software can read and write to these bits
read-only (r or R) Software can only read these bits
write-only (w or W) Software can only write to this bit. Reading the bit returns the reset value
read/write-once (RWOnce) Software can read these bits but write is only allowed once
read/clear (rc_w1 or RWC1)
Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on the bit
value
read/clear (rc_w0 or RWC0)
Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on the bit
value
read/clear by read (rc_r or RC)
Software can read this bit. Reading this bit automatically clears it to ‘0’. Writing ‘0’ has no
effect on the bit value
read/set (rs or RWS1) Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value
read-only write trigger (rt_w or
RWH)
Software can read this bit. Writing ‘0’ or ‘1’ triggers an event but has no effect on the bit
value
toggle (t or RWT1) Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect
Reserved (Res.) Reserved bit, must be kept at reset value
1.3 Glossary
This section gives a brief definition of the abbreviations used in this document:
The SoC integrates the SWD debug port (SWD-DP) which provides a 2-pin (clock and data) interface based on
the serial wire debug (SWD) protocol.
• Word: data/instruction of 32-bit length
• Half word: data/instruction of 16-bit length
• Byte: data of 8-bit length
• Double word: data of 64-bit length
• AHB: advanced high-performance bus
• APB: advanced peripheral bus
• CPU: refers to the Cortex
®
-M0+core
RM0529
Documentation conventions
RM0529 - Rev 2
page 2/726